Cisco packet switching

Here is the short description of what happens at physical level with those three switching methods:

There are the following components in shared memory router:
1. Central CPU - RISC processor in older routers or custom ASIC in newer.
2. Interface ASIC - responsible for receiving/sending packets from/to physical media.
3. Memory - Divided between main memory accessible by central CPU and iomem accessible by interface ASICs.

Process switching:
1. Packet arrives at ingress interface.
2. Ingress ASIC puts packet to iomem and interrrupts main CPU.
3. Main CPU copy packet from iomem to main memory.
4. IOS routing process checks routing table and decides which interface is egress.
5. Packet's L3 and L2 headers are modified and packet is copied to iomem into egress interface output queue.
6. Egress ASIC gets packet from the queue and sends.

Fast switching:
1. Packet arrives at ingress interface.
2. Ingress ASIC puts packet to iomem and interrrupts main CPU.
3. Main CPU copy packet from iomem to main memory.
4. IOS checks if this dest is already in cache-memory. If so all L3 and L2 information is there. If not IOS routing process is invoked and result is copied into fast cache.
5. Packet's L3 and L2 headers are modified and packet is copied to iomem into egress interface output queue.
6. Egress ASIC gets packet from the queue and sends.

CEF switching
1. Packet arrives at ingress interface.
2. Ingress ASIC puts packet to iomem, checks FIB and determines next-hop entry in adjacency table.
3. If packet is CEF-switchable modify L3 header and replace L2 header with the header from adjacency table. If not CEF switchable fallback to fast switching or process switching.
4. iomem area that contains packet is linked to the output queue of egress ASIC.
5. Egress ASIC gets packet from the queue and sends.

There are some nuances but above is basic idea of what happens. Notice that with CEF central CPU and main memory don't get involved in the switching process.
High-end routers work in the similar way but instead of central CPU and memory line-card's CPU and memory are used for the dCEF.

source: https://learningnetwork.cisco.com/message/22503#22503